1. Field of the Invention
The present invention relates to a semiconductor memory device and a method of controlling timing related to operation thereof.
2. Description of the Related Art
Miniaturization of semiconductor memory devices such as DRAM (Dynamic Random Access Memory) is in progress every year. As the miniaturization proceeds, an inter-wiring distance in a semiconductor memory device gets smaller and hence coupling capacitance increases. This increase in coupling capacitance can be a cause of malfunction due to noise.
Particularly in DRAMs, since the area of a cell decreases along with progress in miniaturization, an inter-wiring distance between bit lines connected to memory cells decreases as well. As a result, capacitance between bit lines becomes large, which increases possibility that malfunction occurs due to noise in a sense amplifier while reading out data stored in the memory cells.
As a method to avoid this problem, confinement type sense amplifier operation is known (for example, refer to Japanese Patent Application Laid-open Nos. Hei 9-63266 and Hei 2-301097). The confinement type sense amplifier operation is realized by connecting bit lines in a sense amplifier and bit lines on a memory cell side to which memory cells are connected via transfer gates, and electrically disconnecting the bit lines in the sense amplifier and the bit lines on the memory cell side for a certain period of time when reading (sensing) data from the memory cells.
Specifically, as shown in FIG. 10, a word line WL is selected (time T11), and data stored in the memory cell is outputted to the bit line. At this time, a control signal MUX for the transfer gate to connect the bit line in the sense amplifier and the bit line on the memory cell side is at a high level (hereinafter shown by “H”) and the transfer gate is in on state, and thereby the bit lines BL0, /BL0 in the sense amplifier and the bit lines BL1, /BL1 on the memory cell side are connected, respectively.
Thereafter, a sense amplifier activation signal LE is set to “H” so as to activate the sense amplifier (time T12). At this time, the control signal MUX for the transfer gates is changed to a low level (hereinafter shown by “L”) so as to turn the transfer gates to off state, thereby disconnecting the bit lines BL0, /BL0 in the sense amplifier and the bit lines BL1, /BL1 on the memory cell side. Accordingly, only amplification of the bit lines BL0, /BL0 in the sense amplifier is performed (see times T12 and T13).
After the amplification of the bit lines BL0, /BL0 in the sense amplifier is completed, the control signal MUX for the transfer gates are turned to “H” again so as to connect the bit lines BL0, /BL0 in the sense amplifier and the bit lines BL1, /BL1 on the memory cell side (time T13). In this way, amplification results in the bit lines BL0, /BL0 in the sense amplifier are transmitted to the bit lines BL1, /BL1 on the memory cell side, thereby restoring data in the memory cell. Subsequently, the word line is turned to a non-selected state (time T14) so as to complete the operation. Note that in FIG. 10, STN is a potential level of a storage node in the memory cell (node connected to a capacitor constituting the memory cell).
By allowing the operation as described above, in the confinement type sense amplifier operation, when potentials on the bit lines are amplified by the sense amplifier, an influence of the capacitance between the bit lines on the memory cell side no longer takes effect, and thus the occurrence of malfunction due to noise can be suppressed.
However, in a semiconductor memory device which performs the conventional confinement type sense amplifier operation, the timing to start a confinement operation, namely, the timing to turn the transfer gates to off state and disconnect the bit lines in the sense amplifier and the bit lines on the memory cell side is fixed. Accordingly, there are problems such that adjustment of deviation from optimum timing generated by manufacturing variability or the like is not possible, adjustment to a severe timing in order to accelerate a defect in evaluation/testing is not possible, and so on.